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Time changes and with it the technology
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yes and no. I haven't decided what timer to use. There are several to choose from:
* number of samples, has historically been used. Pretty useless.
* number of ssc_clock-ticks. Used in iso14443a. Uses all timers, depends on FPGA clock and FPGA-mode.
* number of microseconds. Has been used, uses up all ARM-timers. Could conflict with other things which uses timers.
* number of 'ticks'. Looks like a good 'generic' candidate.
The iso14443a timers are extremely finetuned, since piwis prng-attack relied on extreme timing. For generic tracing, I think it's ok with just some kind of decent timer. I don't know which I'll use, so I just used 0 for the moment. Previously, there was no timiing info at all on 'hf 14b list' (correct me if I'm wrong).
The demodulation and modulation is done by the FPGA with a clock based on the 13,56MHz XTAL. Therefore the ssc_clock should be the only reasonable choice. All other clocks are not in sync with whatever happens in the FPGA and "on air".
Added more commands.
When parsing snooped bytes the real command in ISO15693 protocol, it is the second byte, the 1st one is a byte containing bit-flags; ex if you have 022001+2bytesCRC the real command is 20 (read block), 02 contains the flags, 01 is the block to read.
Last edited by asper (2015-02-05 14:06:09)