Research, development and trades concerning the powerful Proxmark3 device.
Remember; sharing is caring. Bring something back to the community.
"Learn the tools of the trade the hard way." +Fravia
Time changes and with it the technology
Proxmark3 @ discord
Users of this forum, please be aware that information stored on this site is not private.
Pages: 1
I think the answer would be in the FPGA code...
In general the raw sample rate will be at whatever rate the ADC (IC8) is being clocked at on pin 12. This signal comes from the FPGA (IC1) pin 46, so I assume it changes based on mode (e.g. slower sample rate for LF operation). Assuming the FPGA doesn't decimate or throw away samples, the plot sample period should be the period of the ADC clock signal.
Of course the FPGA author should clear this up for sure...